Jessica Bhat

Jessica Bhat is a Senior Validation Engineer at Synopsys Inc, where they focus on power integrity analysis for Die IR Drop, EM, and power grid analysis using Ansys RedHawk-SC. Previously, Jessica worked at Intel Corporation as part of the Physical Design team, developing skills in PNR using Cadence Innovus and gaining knowledge in STA and synthesis with Cadence Genus. Jessica earned a Bachelor of Technology in Electronics and Communication Engineering from Shri Mata Vaishno Devi University and a Master’s degree in VLSI Design from Thapar Institute of Engineering & Technology.