Jill Yu

Jill Yu is a Senior Application Engineer at Synopsys Inc., where they focus on customer SOC design bring-up on a multi FPGA-based platform. They have over four years of experience in FPGA-based prototyping and emulation, coupled with more than two years in ASIC IP design and system integration, and one year of experience in ASIC power analysis. Previously, Jill worked as a Senior IC Design Engineer at MediaTek, specializing in FPGA/HAPS prototype integration and ASIC low power analysis, and as a Digital Design Engineer at Realtek Semiconductor Corp., where they contributed to digital system design and chip integration. Jill holds a Master of Science degree in Communication Engineering from National Taiwan University and a Bachelor of Science in Electrical Engineering from Tatung University.