Jing Fu

Jing Fu is a Principal Engineer specializing in ASIC digital design, with extensive experience in verification engineering. They began their career as an FPGA/ASIC Designer at Nortel Networks from 1997 to 1999 and have since held various positions, including Senior Verification Engineer at Extreme Packet Devices and PMC-Sierra, and Senior Verification Lead at Coveloz Consulting Ltd. Currently, they are employed as a Senior Staff Verification Engineer at both Xilinx and Synopsys Inc. Jing obtained their Electrical Engineering degree from Carleton University in 1997.