Jithin Ratheesan is a Senior Design Engineer at Synopsys Inc, where they focus on timing and methodology development. With a Bachelor of Technology in Electrical, Electronics and Communications Engineering from Cochin University of Science and Technology and a Master of Technology in VLSI Design from Amrita School of Engineering Coimbatore, Jithin has built a diverse career. They have previously held positions as a Design Engineer at Spontey and Wave Computing, a Senior Engineer at Qualcomm, and a Senior Design Engineer at RealSilicon. From 2016 to 2019, Jithin worked as a contractor at INVECAS.
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