Jun Wang

Jun Wang is currently a Senior Manager in Research and Development at Synopsys, where they have been a leader and core developer of the electrical-aware design flow for the Custom-Compiler platform since 2008. With over a decade of experience, Jun has contributed to the integration of real-time parasitic extractions in circuit design and supports leading-edge semiconductor design rules. They hold three patents and have authored more than ten academic papers on circuit design and semiconductor lithography enhancement. Jun earned a Bachelor’s degree and a Master of Engineering in Electronic Engineering and Electronic Design Automation from Shanghai Jiao Tong University, and a Doctorate in Semiconductor from The University of Hong Kong.