Karan Chauhan is currently an R&D Staff Engineer at Synopsys Inc., having previously held positions as a Senior Design Verification Engineer and a Design Verification Engineer at Truechip Solutions. With a strong foundation in System Verilog and UVM, Karan has hands-on experience in verification IP development and has provided support for various customer queries. Karan earned a Bachelor of Technology in Electrical, Electronics, and Communications Engineering from Aravali College of Engineering and Management in 2018.
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