Karthik KS

Karthik KS is currently a Staff Design Engineer at Synopsys Inc, where they focus on DDR design. Previously, they held roles as a Senior Design Engineer and SoC Design Engineer, contributing to PCIe and DDR projects at Chelsio Communications and Synopsys. Karthik began their career as an ASIC Design Engineer at LSI, specializing in PCIe, before moving on to IP Design Engineering at Terminus Circuits. They earned a Master's Degree in VLSI Design from the Manipal Institute of Technology. Karthik's expertise includes RTL/IP design, debugging, synthesis, and various digital design protocols.