Keyur Patel

Keyur Patel is a highly skilled engineering professional specializing in ASIC digital design and verification, currently serving as a Staff Engineer at Synopsys Inc since August 2024. Prior to this role, Keyur worked as a Senior Design Verification Engineer at Tech Mahindra Cerium Pvt Ltd from April 2023 to July 2024, collaborating with INTEL. Keyur's extensive experience includes positions at eInfochips (An Arrow Company) and PerfectVIPs, where expertise in verification engineering was developed. Keyur began the professional journey as a VLSI Design & Verification trainee at Indicus Technology. Educationally, Keyur holds a Master of Engineering in Electronics and Communications with a focus on VLSI and Embedded System Design Engineering from Gtu Pg School, as well as a Bachelor of Engineering in Electronics and Communications Engineering from Merchant Engineering College.