Kushal Varshney is a Senior Analog & Mixed Signal Layout Design Engineer at Synopsys Inc., currently working in the Standard Cell & Custom Cell Layout team. With a Master of Technology in Microelectronics from the Birla Institute of Technology and Science, Pilani, Kushal previously served as an Application Engineer at Cadre Design Systems, where they provided technical and commercial support for various design tools. Their educational background includes a Bachelor's degree in Electronics & Communication Engineering from Inderprastha Engineering College and a high school education at Saraswati Vidya Mandir Senior Secondary School, Etah.
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