Malay Saha is a Memory Design Engineer currently serving as a R&D Staff Engineer at Synopsys. They previously held roles at Synopsys, including Sr. Supervisor R&D Engineering and R&D Engineer II, showcasing a strong background in research and development. Prior to Synopsys, Malay worked as a Memory Design Engineer at DXCorr Design Inc. They completed their education with a Master’s Degree in Microelectronics & VLSI from Heritage Institute of Technology and a B.Tech in Electronics & Communication Engineering from JIS College of Engineering.
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