Manas Dewangan is a Principal Engineer at Synopsys, bringing 15 years of extensive experience in designing, developing, and testing high-performance compiler tools using C/C++ for Verilog/SystemVerilog in Linux. Previously, from 2016 to 2020 at Synopsys, they held various roles, culminating in their position as a Staff R&D Engineer, where they significantly enhanced performance through advanced debugging techniques and algorithm implementations. They possess strong expertise in distributed systems and are passionate about technologies such as machine learning and cloud systems. Manas earned a Master of Technology in Computer Science from the Indian Institute of Technology, Guwahati, and a Bachelor of Engineering from Rajiv Gandhi Prodyogiki Vishwavidyalaya.
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