Manasy M

Manasy M is currently an ASIC Design Verification Engineer, Sr 1 at Synopsys Inc, specializing in digital verification. Previously, Manasy worked as a Staff Digital Verification Engineer and as a Design Verification Engineer at ams OSRAM. Manasy also gained valuable experience as a digital verification intern at ams AG, focusing on verification using System Verilog and UVM-based methodologies. Manasy holds a Master's Degree in VLSI design from Amrita School of Engineering, Amritapuri.