Mathavan K is an ASIC RTL Design engineer who is currently a Senior Engineer in ASIC Digital Design at Synopsys Inc since 2025. Previously, Mathavan worked as a Design Engineer at SmartDV Technologies from 2020 to 2023, where they contributed to ASIC IP RTL Design and led multiple ASIC IPs licensed to over 10 customers. Mathavan also gained experience as an Engineer in RTL Design at Proxelera in 2025. They hold a Diploma in Electronics and Communication Engineering from Nachimuthu Polytechnic College, which they completed in 2020.
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