Mathew George

Mathew George has extensive experience in the field of engineering, with a career spanning over a decade. Mathew started as a Senior Engineer in Design and Applications at Larsen & Toubro Limited, where RF Front End implementations on Xilinx FPGAs were a key focus. Following this, Mathew served as an Application Engineer-2 at Lattice Semiconductor, providing applications support and developing reference designs for FPGA and CPLD products. Currently, at Synopsys, Mathew holds the position of Manager in R&D, leading the architecture and design of various FPGA-based IPs and system solutions, with a particular emphasis on DSP IP development and testing for quality and performance. Mathew holds a BTech in Electronics and Communications from Cochin University of Science and Technology and completed an Intermediate in Mathematics, Physics, Chemistry, and English at St. Peter's College, Agra.