Matthew Wille

Matthew Wille is currently a Principal R & D Engineer at Synopsys, Inc, specializing in NVMe VIP and TestSuite verification environment development. They previously held positions as a Staff IC Design Engineer at LSI and as a Principal Design and Verification Engineer at FirstPass Engineering, where they managed development of simulation environments and improved scheduling efficiencies. Prior to those roles, Matthew contributed to system-level simulation environments at Marvell Semiconductor and engaged in ARM core design and verification at Intel Corporation. They earned a Bachelor of Science degree in Electrical Engineering from the University of Minnesota.