Mayank Jain

Mayank Jain is a highly experienced professional in the semiconductor industry, currently serving as a Senior Architect and Sr. Manager in R&D at Synopsys Inc since November 2012. With expertise in technology mapping, logic synthesis, and physical synthesis optimization for timing, area, and power, Mayank has significantly contributed to advancements in the field. Prior to Synopsys, Mayank worked at Mentor Graphics from September 2011 to November 2012, focusing on logic synthesis optimization and technology mapping for emulation. Earlier experience includes a role at Magma Design Automation from May 2007 to September 2011, specializing in formal verification and logic synthesis optimization, and a position as Lead Engineer at Atrenta India Pvt Ltd from 2002 to 2007, where formal verification tools for various verification aspects were developed.