Meetee Desai

Meetee Desai is a Staff Engineer at Synopsys, specializing in ASIC digital design. With a distinguished understanding of the VLSI design and verification process, Meetee has hands-on experience in hardware languages like Verilog and System Verilog, as well as scripting languages such as Perl. They have previously contributed as an intern at Scalable Systems Research Labs Inc., where they enhanced test bench components and developed automation scripts. Meetee holds a Master of Science in Electrical Engineering from California State University, Los Angeles, and a Bachelor's degree in Computer Engineering from Gujarat Technological University.