Megha Jindal is a Senior Staff R&D Engineer at Synopsys, where they specialize in C, C++, data structures and algorithms, as well as RTL languages such as Verilog and VHDL. Previously, Megha worked as a Principal Software Engineer at Cadence Design Systems from 2017 to 2021, contributing to projects including the development of the 'IPX-BUILDER' tool. Megha holds an M.Tech in Computer Science from the Indian Institute of Technology, Delhi, and a Bachelor's degree in Computer Science from Galgotias College of Engineering and Technology.
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