Megha U is a Staff Engineer specializing in Layout Design with extensive experience in the semiconductor industry. They have a strong background in analog layout engineering, including full custom layout design and memory layout, across various technology nodes from 3nm to 180nm. Megha has previously held positions as a Senior Engineer at Sankalp Semiconductor and a Layout Engineer at SmartSoC Solutions Pvt Ltd. Currently, they serve as a Sr AMS Layout Design Engineer at Synopsys Inc, where they leverage their expertise in FinFET, planar MOSFET, multi-patterning processes, and reliability issues.
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