Michael Zieglmeier is a Principal Signal and Power Integrity Engineer at Synopsys, where they focus on signal integrity for high-speed and large parallel interfaces. With previous experience as a Senior Signal Integrity Engineer at Synopsys, they specialized in characterizing DDR memory IP. Prior to this, they held various roles at PMC-Sierra Inc., including Validation/SI Engineer/Leader/Manager, and worked as a Signal Integrity Engineer at Virage Logic. Michael earned their education at the University of Alberta from 1980 to 1985.
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