Mohit Arora

Mohit Arora is a Senior Staff RnD Engineer at Synopsys Inc, specializing in Zebu emulation and memory IPs. With over 12 years of experience, they have developed synthesizable memory models for functional verification, focusing on various memory technologies including DDR5 and NAND Flash. Previously, Mohit held positions as a Design Engineer at Truechip and as a Lead Member of Technical Staff at Siemens EDA, where they contributed to advancements in RTL modeling and protocol validation. Their expertise includes deep knowledge of Verilog, SystemVerilog, and UVM, enabling them to ensure accurate emulation of real-world memory behavior.