Nandini Singh is an R&D Senior Engineer at Synopsys Inc, contributing to advanced engineering projects since June 2022. Previous experience includes an R&D Engineer-I role and a Research Intern position at Indira Gandhi Delhi Technical University for Women, where schematic functionality testing and layout verification for BGR circuits in Cadence Virtuoso were performed. Additionally, an internship at the Defence Research and Development Organisation involved designing a MATLAB app for analyzing the impact of Self-Screening Jammers on Radars. Early roles also included simulation work on Recyclic Folded Cascode circuits and coordination at Innerve. Nandini Singh is pursuing a Master of Technology from BITS Pilani and holds a Bachelor of Technology in Electronics and Communications Engineering from Indira Gandhi Delhi Technical University for Women.
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