Narendra Chauhan

Narendra Chauhan is currently a Layout Manager at Synopsys Inc, specializing in memory layout design with approximately 15 years of experience in the VLSI industry. Previously, they served as a Project Lead at Intel, directing layout development for multiple chip releases, and held senior engineering roles at VirageLogic, LSI Corporation, and Synopsys. Narendra possesses a Master's in VLSI from Kurukshetra University and an MTech in Microelectronics from BITS Pilani's Work Integrated Learning Programmes. Their expertise includes physical/backend design, full custom layout, and memory compiler design.