Nikhil Vaidya is a Staff R&D Engineer at Synopsys (India) EDA Software Private Limited, specializing in memory compiler characterization across various technology nodes and proficient in specialized tools such as HSpice, Cadence Virtuoso, and ModelSim. Prior to this role, Nikhil co-founded Technohornet Services Pvt. Ltd. from 2016 to 2018. Nikhil earned a Bachelor's degree in Electronics and Telecommunication Engineering from P.R. Patil College of Engineering and Technology (2008-2012) and a Master's degree in VLSI Design from Visvesvaraya National Institute of Technology (2013-2016).
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