Parv Arora

Parv Arora is a Staff Engineer at Synopsys, with extensive experience as a Senior Static Timing Analysis Engineer, previously with Qualcomm. While at Qualcomm, Parv led the DDR block to ensure timing closure and high-performance design. Parv holds an M.Tech in VLSI & Embedded Systems from IIIT Delhi and has a solid background in full-flow STA, DDR interface timing, and cross-functional collaboration. Currently, Parv focuses on multiple PrimeTime feature validations and testing, demonstrating a strong passion for robust and timing-closure-driven designs in advanced technology nodes.