Patrick Pereira

Patrick Pereira is a Senior Manager of ASIC Digital Design at Synopsys, where they have worked since 2014 on mixed-signal designs implemented in sub-nanometer nodes. They have extensive experience in defining and implementing digital blocks for mixed-signal IPs, RTL development, and verification using Verilog and System Verilog under UVM methodology. Patrick has also led firmware projects for SERDES links and has over four years of experience in firmware from specification to verification. Previously, they taught basic electronics to secondary school students as a Summer Monitor at INESC-ID and served as Vice President of the Núcleo de Estudantes de Engenharia Electrónica while pursuing a Master’s degree in Electronics Engineering at Instituto Superior Técnico.