Pawan Gupta has extensive experience in ASIC digital design engineering, currently serving as Staff ASIC Digital Design Engineer at Synopsys Inc. since February 2020. Previous roles include Senior Member of Technical Staff at INVECAS, General Member of Technical Staff at Terminus Circuits Pvt Ltd, and Senior RTL Design Engineer at Altior Inc., with a focus on networking and storage. Pawan's expertise encompasses third-party IP integration, specifically with Altera PCIe and PLDA EzDMA, and Pawan has a strong background in IP development, encompassing design specifications, technical documentation, and mentoring teams. Pawan holds a Master of Science in Electronics from Guru Ghasidas University.
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