Phil Baraona

Phil Baraona is a seasoned software engineer and senior R&D manager with a strong background in computer engineering. They began their career at Chrysalis from 1998 to 1999 as a developer on the VHDL compiler team, followed by a role at Avant! from 1999 to 2002, where they led projects on the compiler team and designed user interfaces for software tools. Since 2002, Phil has worked at Synopsys as a Senior R&D Manager for Formality, where they lead a datapath verification team and drive advancements in low-power design verification. Phil is currently pursuing both a PhD and a BS in Computer Engineering at the University of Cincinnati.