Pradeep Garg

Pradeep Garg is a seasoned VLSI specialist with over 11 years of experience in RTL design and verification. They have held various positions, including Engineer at ELCOM Innovations, where they designed RTL for telecom base systems, and Lead Engineer at HCL Technologies, where they managed UVM-based verification projects. Previously, Pradeep worked at STMicroelectronics and is currently engaged as an ASIC Digital Design Staff Engineer at Synopsys Inc in Noida, Uttar Pradesh, India. Pradeep holds a B.Tech in Electronics & Communication from Jaipur Engineering College and a PG Diploma in VLSI & Embedded System Design from CDAC Noida.