Prasanth T.S is an experienced Senior Research and Development Engineer with a demonstrated history in the computer software industry. Prasanth holds a Master of Science (MS) in VLSI CAD from Manipal University, where they studied from 2012 to 2014, and a B.Tech in Computer Science & Technology from the Royal College of Engineering & Technology, completed in 2007. Currently, Prasanth serves as an R&D Manager at Synopsys Inc, having previously worked as a Senior Engineer in R&D Services at MindTree Ltd. and as a Senior R&D Engineer at Synopsys. Prasanth is skilled in debugging, C, C++, Verilog, SystemVerilog, and VLSI.
This person is not in the org chart
This person is not in any teams
This person is not in any offices