Preetam Dalabehera

Preetam Dalabehera is an ASIC Design Verification Staff Engineer at Synopsys, specializing in the verification of various design IPs for 5G NR Physical layer channels. With a total of three years of experience in Design and Verification, they previously worked as a Product Development Engineer at WiSig Networks, developing UVM-based test benches and reference models. Preetam has also served as a Project Associate at 5G Testbed IIT-Hyd and completed training as a Design Verification Trainee at Maven Silicon. They hold an M.Tech in VLSI from Vellore Institute of Technology and a B.Tech in Electrical, Electronics, and Communications Engineering from GITAM University.