Pulumati Chidananda

Pulumati Chidananda holds an MTech in Microelectronics and VLSI Design from the National Institute of Technology Silchar, which was completed in 2023. They have held roles as a Physical Design Engineer at VEDA IIT and Soctronics, and as a DFT Engineer at Intel Corporation from 2022 to 2023. Currently, Pulumati works as a Senior Engineer in ASIC Physical Design at Synopsys Inc, starting in 2025. They earned a BTech in Electronics and Communications Engineering from Keshav Memorial Institute of Technology in 2019.