R Pawan Kumar

R Pawan Kumar has extensive experience in the semiconductor industry, beginning as a Physical Design Trainee at Semiconductor Laboratory under the Department of Space (ISRO) from July 2015 to June 2016, where R Pawan Kumar designed radiation-hardened Phase-Locked Loops for space applications. Following this, R Pawan Kumar worked as a Physical Design Engineer at Qualcomm from September 2017 to April 2021, focusing on advanced 5nm and 7nm chipsets with integrated 5G modem capabilities, demonstrating expertise in timing analysis and ECO generation. R Pawan Kumar also gained experience as a Design Engineer at Si2chip Technologies Pvt. Ltd. during the same period, working with multiple process technologies. After a brief training stint at the Institute of Silicon Systems Pvt. Ltd. in early 2017, R Pawan Kumar has been serving as an ASIC Physical Design Senior Staff Engineer at Synopsys Inc. since February 2025. Education includes a Master's Degree in VLSI Design from the Centre for Development of Advanced Computing and a Bachelor's Degree in Electronics and Communications Engineering from Jawaharlal Nehru Technological University, both achieved with distinction.