Rachit Garg

Rachit Garg has over seven years of experience as a VLSI physical design engineer, specializing in synthesis, place and route, clock tree synthesis, and timing signoff at leading technology companies including Intel and Synopsys. Rachit began their career as a Design Automation Engineer Trainee at NXP Semiconductors and went on to serve as a SoC Design Engineer at Intel Corporation. Currently, Rachit is a Staff Physical Design Engineer at Synopsys while also holding the position of Senior Physical Design Engineer at MaxLinear. Rachit earned an MBA in Human Resources Management from Dayalbagh Educational Institute and a Bachelor of Technology in Electrical, Electronics, and Communications Engineering from Meerut Institute of Technology.