Rahul Gope is a Staff Engineer R&D at Synopsys Inc with over 8 years of experience in the full RTL-to-GDSII flow, emphasizing timing, power, and congestion closure. They successfully delivered tapeouts at 7nm and completed three at 4nm, 3nm, and gained hands-on experience at 6nm, 3nm, and 2nm. Previously, Rahul worked at Synapse Design Inc. and Qualcomm as a Physical Design Engineer and Senior Physical Design Engineer, respectively. Currently, they are pursuing a Bachelor of Technology in Electronics and Instrumentation Engineering at Dr. B.C. Roy Engineering College and a Master of Technology in Microelectronics at Birla Institute of Technology and Science, Pilani.
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