Rajesh Arsid

Rajesh Arsid is a Principal Engineer at Synopsys, specializing in ASIC physical design. With extensive experience across various companies, including roles as a Senior Physical Design Engineer at Seagate and Technical Lead at Capgemini, Rajesh has demonstrated expertise in Place-and-Route implementation, timing closure, and physical verification. Previously, Rajesh served as an R&D Engineer at LSI Corporation and as a Physical Design Engineer at PMC-Sierra and Cyient, honing skills in full-chip integration and power analysis. Rajesh earned a Master's degree in Electronics & Communications from Napier University and continues to contribute to high-performance semiconductor solutions.