Ramesh Hanchinal is an experienced Senior Engineer currently serving as an ASIC Digital Design Manager at Synopsys Inc and Chair of the UniPro Specification Development Work Group. They have a demonstrated history of working in the computer software industry with expertise in PCIe, MIPI protocols, Universal Verification Methodology (UVM), and SystemVerilog. Ramesh's prior experience includes roles at FTD as a Design Engineer, Sasken Technologies Limited as a Hardware Design Engineer, and various engineering positions at Synopsys Inc from 2009 to 2021. They hold a Bachelor of Engineering in Electronics and Communication Engineering from Karnataka University, Dharwad.
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