Ramesh Kumar SG

Ramesh Kumar SG is an ASIC Design Engineer with over three years of experience in Verilog RTL design. They have worked extensively with protocols such as PCIe and AMBA BUS, showcasing skills in RTL coding, linting, and timing closure. Currently, Ramesh is a Senior ASIC Digital Design Engineer at Synopsys Inc, having previously held a position at SmartDV Technologies. Ramesh earned a Bachelor of Engineering in Electronics and Communications Engineering from Mepco Schlenk Engineering College.