Ramesh Sathianathan

Ramesh Sathianathan is a seasoned professional in the technology sector, currently serving as Group R&D Director for the Synopsys Design Group since April 2019. Prior experience includes a tenure as Director of Engineering in the Design Verification Technology division at Mentor Graphics from September 2004 to April 2019, and Director of Engineering and Staff Engineer roles at 0-In Design Automation between September 1997 and September 2004. Ramesh's career began at Synopsys as a Senior Software Engineer from June 1994 to September 1997. Ramesh holds a PhD in Computer Science and an M.Sc in Electrical Engineering from Stony Brook University, where studies were completed from 1988 to 1994 and 1986 to 1988, respectively, as well as a B.Tech in Electrical Engineering from the Indian Institute of Technology, Kanpur, obtained from 1982 to 1986.