Rani Paga is a Senior Layout Engineer at Synopsys with over 3.5 years of experience specializing in standard cell layout across advanced nodes, including 55nm to 2nm technologies. Previously, Rani worked as a Senior Engineer at Eximietas Design, focusing on SerDes custom layout projects and digital block floor planning. Rani holds a Master's degree in Electronics and Communications Engineering from the National Institute of Technology, Tiruchirappalli, and a Bachelor's degree from the National Institute of Technology Surat. Their expertise encompasses a wide range of layout techniques and tools, contributing significantly to projects involving various major semiconductor manufacturers.
Location
Khammam, India
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