Rashmi Saini

Rashmi Saini is a Senior Analog Design Engineer at Synopsys, specializing in SERDES and high-speed protocol design. Currently, Rashmi is pursuing a Master of Technology in Microelectronics and VLSI design at BITS Pilani, while previously earning a B.Tech in Electrical, Electronic, and Communications Engineering from Indira Gandhi Delhi Technical University for Women. Rashmi has experience as a Research Intern and Summer Intern, working on machine learning projects, and has held leadership roles in IEEE IGDTUW. At Synopsys, Rashmi has contributed to the design of regulator circuits and biasing blocks using advanced technology nodes.