Rehaman Sheik is currently a Staff Engineer at Synopsys, focusing on Formal Low Power Tool development in the EDA domain using C++, UPF, Verilog, and Tcl. With over 12 years of IT experience and more than 3 years in Formal Verification and tool development, Rehaman has garnered extensive expertise in C/C++ and various aspects of formal verification tools. Rehaman previously held positions at Robert Bosch Engineering and Business Solutions, HARMAN Connected Services, and Siemens Technology India, contributing significantly to technical projects throughout their career. Rehaman earned a Bachelor's degree in Electronics and Communication Engineering and a PG Diploma in Embedded Systems Design.
This person is not in the org chart
This person is not in any teams
This person is not in any offices