Rekha Adepu

Rekha Adepu is a skilled ASIC Digital Design Manager at Synopsys India Pvt Ltd, having transitioned from a Staff Engineer role to a Senior II Engineer at Synopsys Inc. Between 2020 and 2024, they specialized in the verification of DDR5 PHY using SystemVerilog and UVM, developing test plans, checkers, and stimulus. Earlier in their career, Rekha worked as an Engineer Trainee at Soctronics, where they integrated and verified data paths, and held various engineering roles focusing on logic design and memory controller verification. Rekha holds a Bachelor of Technology in Electrical, Electronics, and Communications Engineering, as well as diplomas in VLSI and Electronics.