RISHAV RAJ

Rishav Raj is a Senior Engineer specializing in ASIC Digital Design at Synopsys, where they focus on digital verification utilizing SystemVerilog and UVM, with expertise in AMBA and SPI protocols. They have hands-on experience in multiple ASIC projects, including the development of SPI controllers. Rishav completed a B.Tech in Electrical and Electronics Engineering from the Birla Institute of Technology, Mesra, and has previously held positions as a Frontend Web Developer and Web Development Intern.