Riya Sachdeva is a Sr Design Engineer I at Synopsys Inc, bringing over 7 years of experience in IO and standard cell characterization, behavioral modeling, and EDA views generation and validation. Riya's career began with an internship at STMicroelectronics in 2013 and progressed through roles at Masamb Electronics Systems and INVECAS, where Riya served as a Senior Design Engineer. Riya also held a design engineer position at Synopsys Inc before advancing to their current role. Riya earned a Master’s degree in VLSI Design from Banasthali Vidyapith in 2014.
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