Rohitash Shukla

Rohitash Shukla is a Principal R&D Engineer with over 8 years of experience in front-end design and verification, specializing in ASIC and FPGA integration. They possess a strong understanding of advanced verification methodologies such as OVM, UVM, and VMM, and have developed multiple constraint random test benches using these techniques. Rohitash has worked on MIPS-32 Processor Core and L2 Cache verification using System Verilog and is proficient in various front-end tools, including NCVerilog and VCS. Currently, they hold the position of Staff R&D Engineer at Synopsys Inc and are pursuing dual master's degrees in Computer Science and Electronics.