Runliang W. is a Senior Analog Design Engineer at Synopsys Inc, where they apply their expertise in analog circuit design, honed during their Master's degree in Electrical and Electronics Engineering from the University of Toronto. Previously, they completed a SRAM design internship at TSMC, gaining hands-on experience with the 7nm process and utilizing automation through developed Perl and Python scripts. Runliang earned a Bachelor of Applied Science in Electrical and Electronics Engineering from The University of British Columbia. They demonstrate strong problem-solving abilities and a commitment to teamwork and efficiency in their professional endeavors.
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