Rushabh Patel

Rushabh Patel is an R&D Staff Engineer with over 7 years of experience in RTL Design for ASICs. They currently work at Synopsys Inc. and have previously held positions as a Senior Silicon Design Engineer at AMD and a Design Engineer at Microchip Technology Inc., where they contributed to various aspects of SoC Video Design and IP development. Rushabh began their academic journey with a Bachelor of Engineering in Instrumentation and Control from Vishwakarma Government Engineering College, followed by a Master of Technology in VLSI Design from Vellore Institute of Technology. They have also gained valuable experience through an internship at Microsemi Corporation.