Sagar Arora currently holds the position of Senior Staff ASIC Design at Synopsys Inc since April 2023, previously serving as Staff Engineer and ASIC Design Sr2 Engineer, focusing on UCIe Chiplet Interconnect, PCIe-UCIe, and CXL-UCIe Controller and Adapter. Prior to this, Sagar worked at Intel Corporation as a Lead Engineer from August 2020 to August 2023, specializing in Ethernet Controllers and Infrastructure Processing Units. At Samsung Semiconductor, Sagar was an Associate Staff Engineer from January 2018 to August 2020, contributing to Security and Cryptography IPs, while earlier experience includes roles at HCL Technologies as a Senior ASIC Engineer and Design & Verification Engineer. Sagar initiated professional development with internships at Indian Railways and Sofcon India Pvt. Ltd. Sagar holds a Master of Technology in Microelectronics from Birla Institute of Technology and Science, Pilani, and a Bachelor of Technology in Electronics and Telecommunications Engineering from the College of Engineering Roorkee.
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