Sagar Mishra is a Staff Engineer in R&D Engineering at Synopsys, where they are currently working with the DFI Verification IP team on LPDDR5 and LPDDR6 projects. Previously, Sagar served as a Software Engineer II at Cadence Design Systems, where they focused on Ethernet Verification IP and supported various customer needs. Their earlier roles included contributions as a Software Engineer I and a Software Engineering Intern, where they developed verification environments and provided customer support for various protocols. Sagar holds a Bachelor of Technology degree in Electronics and Communications Engineering from Rajasthan Technical University, which they completed in 2018.
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